TMDXEVM5515【PDF 14/159 页】EVAL MODULE DSP FOR C55XX

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SPRS645F – AUGUST 2010 – REVISED OCTOBER 2013

2.4

2.4.1

Pin Assignments

Extensive pin multiplexing is used to accommodate the largest number of peripheral functions in the

smallest possible package. Pin multiplexing is controlled using software programmable register settings.

For more information on pin muxing, see Section 3.7 , Multiplexed Pin Configurations of this document.

Pin Map (Bottom View)

Figure 2-2 shows the bottom view of the package pin assignments.

P

N

EM_DQM1

EM_A[15]/

GP[21]

DV DDEMIF

EM_SDCKE

DV DDIO

LCD_

EN_RDB/

SPI_CLK

LCD_

CS0_E0/

SPI_CS0

LCD_

CS1_EN1/

SPI_CS1

LCD_

RW_WRB/

SPI_CS2

LCD_RS/

SPI_CS3

LCD_D[0]/

SPI_RX

LCD_D[1]/

SPI_TX

LCD_D[2]/

GP[12]

LCD_D[3]/

GP[13]

DV DDIO

LCD_D[4]/

GP[14]

LCD_D[5]/

GP[15]

LCD_D[6]/

GP[16]

LCD_D[7]/

GP[17]

LCD_D[8]/

I2S2_CLK/

GP[18]/

SPI_CLK

LCD_D[9]/

I2S2_FS/

GP[19]/

SPI_CS0

LCD_D[10]/

I2S2_RX/

GP[20]/

SPI_RX

LCD_D[11]/

I2S2_DX/

GP[27]/

SPI_TX

LCD_D[12]/

UART_RTS/

GP[28]/

I2S3_CLK

LCD_D[13]/

UART_CTS/

GP[29]/

I2S3_FS

LCD_D[14]/

UART_RXD/

GP[30]/

I2S3_RX

LCD_D[15]/

UART_TXD/

GP[31]/

I2S3_DX

DV DDIO

MMC0_D1/

MMC0_CMD/

MMC1_D1/

MMC1_CLK/

MMC1_D0/

M

L

K

J

H

EM_A[14]

EM_A[13]

EM_A[12]/

(CLE)

EM_A[8]

EM_WE

EM_D[5]

EM_A[10]

EM_A[11]/

(ALE)

EM_A[9]

EM_A[7]

EM_SDCLK

EM_D[12]

EM_D[14]

EM_A[20]/

GP[26]

EM_D[7]

EM_CS3

EM_D[4]

EM_D[13]

EM_D[15]

EM_WAIT5

EMU1

CV DD

EM_D[6]

DV DDEMIF

DV DDEMIF

TCK

EMU0

EM_WAIT3

CV DD

V SS

TDO

TDI

DV DDIO

V SS

DV DDEMIF

XF

TMS

V SS

V SS

CV DD

TRST

MMC0_D0/

I2S0_DX/

GP[2]

V SS

V SS

USB_

V SSA1P3

I2S0_RX/

GP[3]

MMC0_CLK/

I2S0_CLK/

GP[0]

CV DD

RSV1

USB_

V DDA1P3

I2S0_FS/

GP[1]

MMC0_D3/

GP[5]

V SS

RSV2

USB_

V SSA3P3

I2S1_RX/

GP[9]

MMC0_D2/

GP[4]

DV DDIO

USB_VBUS

USB_

V DDA3P3

I2S1_CLK/

GP[6]

MMC1_D3/

GP[11]

V SS

USB_V DD1P3

USB_V SS1P3

I2S1_DX/

GP[8]

MMC1_CMD/

I2S1_FS/

GP[7]

MMC1_D2/

GP[10]

USB_DM

USB_DP

G

EM_WAIT4

EM_A[18]/

GP[24]

EM_D[0]

EM_A[19]/

GP[25]

DV DDEMIF

V SS

V SS

USB_V DDPLL

USB_R1

USB_V SSREF USB_V SSPLL USB_V DDOSC

USB_MXI

USB_MXO

F

E

D

C

B

A

EM_A[6]

EM_A[2]

EM_A[5]

EM_A[4]

EM_BA[1]

EM_BA[0]

1

EM_A[17]/

GP[23]

EM_A[16]/

GP[22]

EM_A[3]

EM_A[1]

EM_A[0]

DV DDEMIF

2

EM_D[2]

EM_D[8]

EM_D[10]

EM_CS4

EM_CS0

EM_CS5

3

EM_D[9]

EM_OE

EM_D[3]

EM_D[11]

EM_SDCAS

EM_CS1

4

DV DDEMIF

EM_D[1]

EM_WAIT2

EM_CS2

EM_DQM0

DV DDEMIF

5

CV DD

DV DDEMIF

RESET

INT0

EM_R/W

EM_SDRAS

6

DV DDIO

INT1

V SS

CLK_SEL

SCL

CLKOUT

7

DV DDRTC

WAKEUP

RTC_

CLKOUT

CV DDRTC

SDA

CLKIN

8

V SS

V SS

V SSA_PLL

V SSRTC

RTC_XI

RTC_XO

9

V SS

DSP_LDOO

GPAIN0

V DDA_PLL

V SSA_ANA

V DDA_ANA

10

USB_V SSOSC

V SS

V SS

GPAIN3

GPAIN2

GPAIN1

11

USB_LDOO

VSS

DSP_

LDO_EN

RSV0

LDOI

ANA_LDOO

12

LDOI

V SS

RSV16

RSV5

BG_CAP

V SS

13

LDOI

V SS

RSV3

RSV4

V SSA_ANA

V SS

14

Figure 2-2. Pin Map

14

Device Overview

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